In apparatus for automatically testing electronic circuits, digital test patterns are stored in memory and used to provide input test sigals applied to nodes of a circuit under test ("CUT"), and the resulting outputs from the CUT are compared with expected outputs. Test apparatus can also include such analog instruments as high frequency and low frequency signal generators to provide analog test signals to the CUT and high and low frequency digitizers and associated capture memory to digitize and store results.
In order to simultaneously provide control signals for the test apparatus and deliver a large number of bits of data to the CUT synchronously with the clocking of the CUT at its high rate, a high speed sequence controller is used to provide the control bits (also referred to as "microcode" herein) and data bits in parallel at high speed. (The microcode plus data bits at a given clock period are referred to as a "vector".) The control bits are included in a random access memory ("RAM") in the sequence controller, for example, 16K deep to provide 16K instruction steps that can be randomly accessed upon providing the appropriate address to the RAM on an address bus (often referred to as a "state bus") controlled by an address generator in the sequence controller. Control bits associated with the various instruments and test pattern memories could also be located in respective microcode RAMs distributed across separate boards and accessed by the state address bus.
When running tests involving a large number of test data, there often are large blocks of vectors in which there are sequential steps of test data to be applied to the circuit under test, and the microcode does not change for a large number of clock periods. Such vectors are referred to herein as "sequential vectors". Where there are conditional statements or jumps in the test program, the system must be able to randomly jump to a state address that does not follow the current address; such vectors are referred to as "nonsequential vectors".
Because of the expense of high-speed static RAM and the large number of data signals used in some test patterns, test data are sometimes stored in bulk in a high-capacity memory of slower, and less expensive, dynamic RAMs, which are used to transfer blocks of test data at one time to reload high-speed static RAMs. For example, Gillette U.S. Pat. No. 4,451,958, discloses an automatic circuit tester in which large blocks of test patterns are loaded from interleaved dynamic RAMs into a first static RAM while a second static RAM is providing test data to the CUT, and the test patterns are then loaded into the second static RAM while the first is providing test data and so on. When writing a control program for the system using the dynamic RAMs to alternately provide test data to alternate static RAMs, the programmer must make sure that he does not have any conditional statements or jumps to steps that are not in the same group loaded into a static RAM at the same time.